Technical Field
The present invention generally relates to semiconductor device fabrication and, more particularly, to field nanowire and nanosheet field effect transistors that have a spacing between channel layers that is greater than a critical thickness of a sacrificial material.
Description of the Related Art
Nanowire and nanosheet transistor devices may be created using silicon germanium as a sacrificial layer formed between layers of silicon. However, due to the lattice mismatch between silicon germanium crystals and silicon crystals, a strain is formed in the sacrificial silicon germanium layers. When the silicon germanium layers are formed to a thickness that is greater than a critical thickness, defects such as dislocations are formed in the stack.
For example, in silicon germanium having a germanium concentration of about 35%, the critical thickness is about 8 nm. Because the spacing between adjacent silicon channel layers is determined by the silicon germanium thickness, the small critical thickness limits the silicon channel spacing. This can make it difficult to pattern gate workfunction metals and form thick gate oxide transistors. The thick oxide gate dielectric pinches off the small gap between silicon channels, leaving no room for the gate workfunction metal. Even with thinner gate dielectrics, it is often advantageous to have different workfunction metals for different kinds of transistor. Removing the workfunction metal from the narrow gap between channels can necessitate an aggressive etch which can create an undesirable undercut between adjacent transistors.